I am trying to configure timer interrupt for Kite processor on Fastmodel.
I have enabled GICD to enable timer interrupt and it is also updating as pending once timer is 0 but to receive it to cpu interface I need to enable it in GICR.
When trying to enable it in GICR, registers are not getting updated when I run simulation. Only GICR_IGROUPR0 is updated. GICR_ISENABLER0 register is not getting updated.
Does anyone have any idea why only 1 register is able to update and not others?
Do I need any specific configuration to use GICR registers? Why only 1 register is able to update?
#define GICC_OFFSET 0x00
#define GICD_OFFSET 0x00
#define GICR_OFFSET 0x0100000
#define GICR_SGI_PPI_OFFSET 0x110000 // for core 0
/* CBAR is read and then the offset for Distributor and CPU Interfaces are added */
#define GICREG(gic, reg) (*REG32(hal_arm_gic_get_base() + (reg)))
/* Redistributor control registor GICR_ */
#define GICR_CTLR (GICR_OFFSET + 0x00)
/* Redistributor for SGI and PPI for core 0*/
#define GICR_IGROUPR0 (GICR_SGI_PPI_OFFSET + 0x80)
#define GICR_ISENABLER0 (GICR_SGI_PPI_OFFSET + 0x100)
#define GICR_ICENABLER0 (GICR_SGI_PPI_OFFSET + 0x180)
#define GICR_ISPENDR0 (GICR_SGI_PPI_OFFSET + 0x200)
#define GICR_ICPENDR0 (GICR_SGI_PPI_OFFSET + 0x280)
#define GICR_ISACTIVER0 (GICR_SGI_PPI_OFFSET + 0x300)
#define GICR_ICACTIVER0 (GICR_SGI_PPI_OFFSET + 0x380)
#define GICR_IPRIORITYR(n) (GICR_SGI_PPI_OFFSET + 0x400 + (n) * 4)
#define GICR_ICFGR0 (GICR_SGI_PPI_OFFSET + 0xc00)
#define GICR_ICFGR1 (GICR_SGI_PPI_OFFSET + 0xc04)
/* distribution regs */
#define GICD_CTLR (GICD_OFFSET + 0x000u)
#define GICD_TYPER (GICD_OFFSET + 0x004u)
#define GICD_IIDR (GICD_OFFSET + 0x008u)
#define GICD_IGROUPR(n) (GICD_OFFSET + 0x080u + (n) * 4u)
#define GICD_ISENABLER(n) (GICD_OFFSET + 0x100u + (n) * 4u)
#define GICD_ICENABLER(n) (GICD_OFFSET + 0x180u + (n) * 4u)
#define GICD_ISPENDR(n) (GICD_OFFSET + 0x200u + (n) * 4u)
#define GICD_ICPENDR(n) (GICD_OFFSET + 0x280u + (n) * 4u)
#define GICD_ISACTIVER(n) (GICD_OFFSET + 0x300u + (n) * 4u)
#define GICD_ICACTIVER(n) (GICD_OFFSET + 0x380u + (n) * 4u)
#define GICD_IPRIORITYR(n) (GICD_OFFSET + 0x420u + (n) * 4u)
#define GICD_ITARGETSR(n) (GICD_OFFSET + 0x800u + (n) * 4u)
#define GICD_ICFGR(n) (GICD_OFFSET + 0xc00u + (n) * 4u)
GIC V3 configuration:
// Check whether GICv3 system registers are available
mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
ubfx r7, r7, #28, #4
cmp r7, #1
bne 2f
// Enable system register accesses
mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
orr r7, r7, #( (1 << 0) | (1 << 3))
mcr p15, 4, r7, c12, c9, 5 @ ICC_HSRE
isb
// SRE bit could be forced to 0 by firmware.
// Check whether it sticks before accessing any other sysreg
mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
tst r7, #ICC_SRE_EL2_SRE
beq 2f
mov r7, #0
mcr p15, 4, r7, c12, c11, 0 @ ICH_HCR
2:
mov R0, #0x1
MRC p15, 0, R0, c12, c12, 6
orr r0, r0, #0x1
MCR p15, 0, R0, c12, c12, 6 // Group 0 Enable
MRC p15, 0, R0, c12, c12, 7
orr r0, r0, #0x1
MCR p15, 0, R0, c12, c12, 7 // Group 1 Enable
After days of search and tries, I found that it is issue in ARM Kite processor itself. ARM has released it untested to start development for partner companies.
Sad to hear this.