How to detect logic gates from scanned images of hand drawn circuits?

Question

we started with scanned images of proper drawn diagrams of logic circuit we were able to separate the logic gates from the scanned image of the circuit however we were not able detect and how to proceed further,we had use python open cv for this ,our code for the above is

import cv2
import numpy as np
from matplotlib import pyplot as plt
img = cv2.imread('logic.png',0)

ret,img2 = cv2.threshold(img,127,255,cv2.THRESH_BINARY_INV)  # converting the image into binary image.
kernel = cv2.getStructuringElement(cv2.MORPH_RECT,(100,3))  # kernel to detect vertical lines
vertical = cv2.morphologyEx(img2, cv2.MORPH_OPEN, kernel)  # applying morphological opening operation to detect vertical lines
vertical = cv2.dilate(vertical,kernel,iterations = 1)   #dilate the vertical lines obtained

kernel2 = cv2.getStructuringElement(cv2.MORPH_RECT,(3,100))   # kernel to detect horizontal lines
horizontal = cv2.morphologyEx(img2, cv2.MORPH_OPEN, kernel2)   # applying morphological opening operation to detect horizontal lines
horizontal = cv2.dilate(horizontal,kernel2,iterations = 1)    #dilate the horizontal lines obtained

cv2.imshow('d',vertical)    # show the vertical imag
cv2.imshow('b',horizontal)  # show the horizontal image

img = img2 -horizontal - vertical   # subtracting horizontal and vertical lines from original image

cv2.imwrite('horizontal.png',horizontal)   
cv2.imwrite('vertical.png',vertical)
cv2.imwrite('result.png',img)


cv2.imshow('last',img)     # show the resulted image after subtraction

kerne = np.ones((3,3),np.uint8)             # kernel to remove the noise from the last image
opening = cv2.morphologyEx(img, cv2.MORPH_OPEN, kerne)  # applying opening morphological operation to remove the noise from the image 
cv2.imshow('opening',opening)               # show the resulted image after removing noise
cv2.imwrite('noise_removal.png',opening)
cv2.waitKey(0)

Check the result below and advise how to proceed further to detect the logic gates from the scanned images of hand drawn circuits?

The result of the code is below :

1) Input Image :

2) Output Image (code result) :

Answer 1

The logic doors all have the same size. I would do that:

1. Connected component labeling of white areas.
2. Separate/isolate
3. Filter the labels by the size.
4. (optional) All the logic doors will touch a tiny white pattern/label on the right.