How to test how does a RISC-V implementation process misaligned data access?

Question

I see some words on riscv-spec-20191213: Loads and stores where the effective address is not naturally aligned to the referenced datatype (i.e., on a four-byte boundary for 32-bit accesses, and a two-byte boundary for 16-bit accesses) have behavior dependent on the EEI.

In other words, EEIs can determine how they process misaligned data access. My question is can we examine the EEIs' behaviours when they meet the misaligned data access?

I have read some materials and test if a SIGBUS signal was raised when misaligned data access using code snippets below.

#include <stdio.h>
#include <stdlib.h>
#include <signal.h>
#include <string.h>
#include <error.h>
#include <errno.h>

void sigbus_handler(int signum) {
    printf("A SIGBUS\n");
}

void init_sigbus() {
    if (signal(SIGBUS, sigbus_handler) == SIG_ERR) {
        perror("Error setting signal handler");
    }
}

int main() {
    long long a = 0x1010101010101010LL;
    long long *pa = &a;
    int *pia = (int *)pa;

    /* this make sure the pointer pia is 0x.....100 */
    pia += 1;

    init_sigbus();

    /* mda */
    long long b = *(long long*)pia;

    return 0;
}

The result is that no SIGBUSs were raised when mda.

Thank you all for your attention!

Edit1:

Below is the screenshot of gdb:

The address of pia is misaligned.