- We assume that in a CPU the cache memory is of type TO WAY SET associative with a size of 16 MB and a line size of 4B for memory addressing the CPU uses 32 bits .
a) Find how many bits are used for the address tagg, cache index, byte offset
b) How many bytes in total are used to store the tagg address in this cache.
c) How many bytes in total are used to store the tagg address in this cache if the memory were fully associative
d) How many bytes in total are used to store the tagg address in this cache in the case of Direct Mept?
I've made these calculations BUT I'M NOT SURE AND NEED A CONFIRMATION IF IT'S OK :
a)
Number of sets = cache size / (line size * associativity)
Number of Sets = (2^24 bytes) / (4 bytes * 2) = 2^21 sets
Number of bits for CACHE INDEX = log2(2^21) = 21
Since the line size is 4B , then the Number of bits for BYTE OFFSET is 2 (i'm not sure !!! )
The number of bits for Address TAG is 32-21-2= 9 ( I'm not sure !!! )
b)
Each cache line consists of the tag address and the data. Since the tag address size is 9
bits and each byte is 8 bits, the tag address can be stored in 9 bits / 8 bits per byte =
1.12 bytes. Since a cache line size is 4 bytes, it will require 2 cache lines to store the
tag address. Therefore, the total number of bytes used to store the tag address in this
cache is 2 cache lines * 4 bytes per cache line = 8 bytes.
c)
In the case of a fully associative cache, the entire cache is used as a single set.
Therefore, the number of sets is equal to 1. The number of bits needed for the cache index is
log2(1) = 0 bits. The remaining bits are used for the address tag, which is 32 - 0 - 2 = 30
bits.
Since the tag address size is 30 bits and each byte is 8 bits, the tag address can be stored
in 30 bits / 8 bits per byte = 3.75 bytes. Since a cache line size is 4 bytes, it will
require 1 cache line to store the tag address. Therefore, the total number of bytes used to
store the tag address in this cache is 1 cache line * 4 bytes per cache line = 4 bytes.
d)
In the case of direct mapping, each set only consists of one cache line. Therefore, the
number of sets is equal to the number of cache lines, which is equal to the cache size
divided by the line size. In this case, there are 16MB / 4B = 2^24 / 2^2 = 2^20 sets.
The number of bits used for the cache index is log2(2^20) = 20 bits.
The remaining bits are used for the address tag, which is equal to the total number of bits
in the memory address minus the number of bits used for the cache index and byte offset. In
this case, it is 32 - 20 - 2 = 10 bits.
Since the tag address size is 10 bits and each byte is 8 bits, the tag address can be stored
in 10 bits / 8 bits per byte = 1.25 bytes. Since a cache line size is 4 bytes, it will
require 2 cache line to store the tag address. Therefore, the total number of bytes used to
store the tag address in this cache is 2 cache line * 4 bytes per cache line = 8 bytes.