Question

How CPUs Use the LOCK Prefix to Implement Cache Locking and ensure memory consistency

score 128 · Answer 1 · 2024-03-15T11:05:42.203000

128

Views

How CPUs Use the LOCK Prefix to Implement Cache Locking and ensure memory consistency

Published on 15 March 2024 at 11:05

score 23 · Answer 2 · 2024-03-05T12:59:25.667000

23

Views

How to check whether the PCIe Memory-mapped BAR region is cacheable or uncacheable

Published on 05 March 2024 at 12:59

score 58 · Answer 3 · 2024-03-04T10:05:52.377000

58

Views

Are RISC-V SH and SB instructions allowed to communicate with the cache?

Published on 04 March 2024 at 10:05

score 16 · Answer 4 · 2024-02-25T20:13:56.770000

16

Views

for remote socket cache-to-cache data transfer, why data homed in reader socket shows higher latency than data homed in writer socket?

Published on 25 February 2024 at 20:13

score 44 · Answer 5 · 2024-02-22T11:30:59.760000

44

Views

Performance implications of aliasing in VIPT cache

Published on 22 February 2024 at 11:30

score 87 · Answer 6 · 2024-02-20T22:39:18.330000

87

Views

Why do fast memory writes when run over multiple threads take much more time vs when they are run on a single thread?

Published on 20 February 2024 at 22:39

score 62 · Answer 7 · 2024-02-15T14:49:52.330000

62

Views

question regarding the behavior of the program in Meltdown attack

Published on 15 February 2024 at 14:49

score 22 · Answer 8 · 2024-02-11T22:41:59.740000

22

Views

Seeking Verification: MIPS Cache Set Update Analysis

Published on 11 February 2024 at 22:41

score 65 · Answer 9 · 2024-02-11T05:31:25.450000

65

Views

OS cache/memory hierarchy: How does writing to a new file work?

Published on 11 February 2024 at 05:31

score 73 · Answer 10 · 2024-02-07T17:48:01.910000

73

Views

Can there be a cache block with the same Tag-ID in different Sets?

Published on 07 February 2024 at 17:48

score 16 · Answer 11 · 2024-02-07T13:27:57.250000

16

Views

is it a way to do a "store" operation without fetching in case of cache miss

Published on 07 February 2024 at 13:27

score 38 · Answer 12 · 2024-02-06T08:42:18.507000

38

Views

why is there a need to stop prefetching to pages when a write happens to it?

Published on 06 February 2024 at 08:42

score 62 · Answer 13 · 2024-01-21T08:56:21.113000

62

Views

is it possible that a cpu has several L3 level caches？

Published on 21 January 2024 at 08:56

score 46 · Answer 14 · 2024-01-19T19:41:09.610000

46

Views

Are 64-byte CPU cache line reads aligned on 64-byte boundaries?

Published on 19 January 2024 at 19:41

score 59 · Answer 15 · 2024-01-17T10:55:22.903000

59

Views

how cpu cache when physical address is not contiguous

Published on 17 January 2024 at 10:55

score 35 · Answer 16 · 2024-01-13T09:38:48.897000

35

Views

What's the difference between those "cache_as_ram.S" in coreboot?

Published on 13 January 2024 at 09:38

score 57 · Answer 17 · 2024-01-12T03:19:41.330000

57

Views

Address tagg, cache index, byte offset

Published on 12 January 2024 at 03:19

score 57 · Answer 18 · 2024-01-11T02:21:28.173000

57

Views

Calculating HIT RATE on a CACHE MEMORY

Published on 11 January 2024 at 02:21

score 62 · Answer 19 · 2024-01-07T19:03:37.670000

62

Views

CPU performance counters in C++ (Mac/PC, Intel)

Published on 07 January 2024 at 19:03

score 56 · Answer 20 · 2023-12-29T00:01:44.520000

56

Views

Matrix multiplication in C# - is there a better way than copying to a jagged array?

Published on 29 December 2023 at 00:01

List Question

How CPUs Use the LOCK Prefix to Implement Cache Locking and ensure memory consistency

How to check whether the PCIe Memory-mapped BAR region is cacheable or uncacheable

Are RISC-V SH and SB instructions allowed to communicate with the cache?

for remote socket cache-to-cache data transfer, why data homed in reader socket shows higher latency than data homed in writer socket?

Performance implications of aliasing in VIPT cache

Why do fast memory writes when run over multiple threads take much more time vs when they are run on a single thread?

question regarding the behavior of the program in Meltdown attack

Seeking Verification: MIPS Cache Set Update Analysis

OS cache/memory hierarchy: How does writing to a new file work?

Can there be a cache block with the same Tag-ID in different Sets?

is it a way to do a "store" operation without fetching in case of cache miss

why is there a need to stop prefetching to pages when a write happens to it?

is it possible that a cpu has several L3 level caches？

Are 64-byte CPU cache line reads aligned on 64-byte boundaries?

how cpu cache when physical address is not contiguous

What's the difference between those "cache_as_ram.S" in coreboot?

Address tagg, cache index, byte offset

Calculating HIT RATE on a CACHE MEMORY

CPU performance counters in C++ (Mac/PC, Intel)

Matrix multiplication in C# - is there a better way than copying to a jagged array?

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