ASIC design - combinational logic

Question

I had an interview a few days back and this was the question they asked me in one of the rounds:

A mux which gives output a when select line is 1 and b when it is 0. The output is represented as C. This has to be implemented with and and not gates only.

I got it almost but was not sure how the output is received finally in combinational ckt. It is a very simple thing I missed here. I gave the select line to an and gate and input a and the select line and the input b through a not gate to another and gate so I got the output as A and B but how can we have one output alone? either a or b?

Answer 1

 C = (A and not(S)) or (B and S)
   = not(not(A and not(S)) and not(B and S))

Answer 2

A input 1, B input 2, S input select line, C output,

C = (A & S) | (A & ~S);

Its simple bro!