In the context of combinatorial logic synthesis (not simulation): When should a function be declared as automatic ? When should a function be declared as static ?
Systemverilog function synthesis - automatic vs static
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A function should never be declared with a
staticlifetime. There is no case where a function would be automatic by default and need to be explicitly declared static. (and this would be illegal do in a class method anyways).There are cases where a function must be declared with automatic lifetime so it cn be called recursively and the arguments won't be overwritten.
This is the part of the subject of my DVCon2021 paper "The Life of a SystemVerilog Variable".