Can't read SDRAM of TI OMAP5912 ARM core using JTAG

Question

I'm trying to connect to OMAP5912 device using XDS560v2 TRAVELER JTAG emulator using Code Composer Studio 7. When connecting to C55x device using Connect Target it successfully stops at an arbitrary RAM point. When using Connect Target on the ARM9 core, it always stops at 0xFFFF0000. Now, when I look at its registers, everything seems fine and I see that the LR is placed around the known firmware location on SDARM e.g. 0x102B1AD4. But! When I access the Memory Browser Of Code Composer Studio 7 and look at the SDRAM location I see only the following chain of bytes "0x00009C46". I tried to switch between CPU memory and physical memory views and nothing helps. Somebody knows what's happening here? Thank you.

Answer 1

Probably there was a bug in Code Composer 7, so I used my own .gel file based on a .gel found on github and it solved the problem. In Code Composer select "New target configuration", then Add STM SDX560V2 Traveler or else. Add bypass of 8, add arm9 core and attach this .gel file, and finally, add c55xx core.

StartUp()
{ }

OnTargetConnect()
{
    disable_watchdog_timer( );
    add_breakpoints();
}

OnHalt()
{
    // Add here your stuff
    GEL_TextOut("R0 %x R1 %x\n",,,,,R0, R1);
    GEL_MemorySave(0xCAFEBABE, 0, 96, "/tmp/memdump.bin",8,0);
    GEL_Go();
}

add_breakpoints()
{
    // Add here your breakpoint
    GEL_BreakPtAdd(0xCAFEBABE);
}

disable_watchdog_timer( )
{
    #define WD_CNTL_TIMER           *( unsigned short* )0xFFFEC800
    #define WD_LOAD_TIM             *( unsigned short* )0xFFFEC804
    #define WD_TIMER_MODE           *( unsigned short* )0xFFFEC808
    #define WDT_WWPS                *( unsigned int* )0xFFFEB034
    #define WDT_WSPR                *( unsigned int* )0xFFFEB048

    WD_TIMER_MODE = 0x00F5;         // Disable Watchdog Timer
    WD_TIMER_MODE = 0x00A0;

    WDT_WSPR = 0xAAAA;              // Disable 32KHz Watchdog
    while ( WDT_WWPS & 0x0010 );
    WDT_WSPR = 0x5555;
    while ( WDT_WWPS & 0x0010 );
}