Changing square waveform duty cycle in VHDL

Question

I created a waveform of 10kHz through the divider in VHDL. CLK is the input clock of 50MHz while clk_new is the output clock at 10kHz. I need to change the clk_new duty cycle of 20%, 40% and 60%. Do you have any suggestion of how to modify the code below?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

ENTITY divider IS
PORT(RST_N : IN std_logic;
     CLK    : IN  std_logic;
     clk_new    : OUT std_logic
     );
END divider;

ARCHITECTURE bhv OF divider IS
SIGNAL i_q  : std_logic_vector(12 downto 0);

BEGIN

clk_new <= i_q(12);

cnt: PROCESS(CLK,RST_N)

 BEGIN
  IF RST_N = '0' THEN
    i_q <= (OTHERS => '0');
  
  ELSIF rising_edge(clk) THEN
    if (i_q = 5000) then
    i_q <= (OTHERS => '0');
    else
    i_q <= i_q + 1;
    end if;
  END IF;   
END PROCESS;    

END bhv;

I tried to set the clk_new signal to less significant bits of i_q but I did not achieve the desired effect. Thank you for helping.