Clash / Haskell 'Unbound implicit parameters' error when building

Question

I am building a simple toggle LED circuit, by following available tutorials online:

Assigning explicit clock, reset and enable arguments to hidden clocks, resets and enables

New Clash FPGA Starter

module LED2 where

-- ref https://hackage.haskell.org/package/clash-prelude-1.6.4/docs/Clash-Tutorial.html

import Clash.Prelude
import Clash.Intel.ClockGen
import Clash.Annotations.SynthesisAttributes

import Clash.Annotations.TH

topEntity ::
  "CLOCK_50" ::: Clock IntelSystem --clk
    `Annotate` 'StringAttr "chip_pin" "R8"
    `Annotate` 'StringAttr "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" ->
  "KEY0" ::: Reset IntelSystem -- reset BTN
    `Annotate` 'StringAttr "chip_pin" "J15"
    `Annotate` 'StringAttr "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" ->
  "KEY1" ::: Signal IntelSystem Bit -- input BTN
    `Annotate` 'StringAttr "chip_pin" "E1"
    `Annotate` 'StringAttr "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\"" ->
  "LED" ::: Signal IntelSystem Bit  -- output LED
    `Annotate` 'StringAttr "chip_pin" "A15"
    `Annotate` 'StringAttr "altera_attribute" "-name IO_STANDARD \"3.3-V LVTTL\""

topEntity clk rst key1 =
    let  (pllOut,pllStable) = altpll @IntelSystem (SSymbol @"altpll50") clk rst
         rstSync            = resetSynchronizer pllOut (unsafeFromHighPolarity pllStable)
    in   exposeClockResetEnable leds pllOut rstSync enableGen
    where
      leds   = mealy ledT (1, False) key1R
      key1R  = isRising 1 key1

ledT (led,mode) key1R = ((led',mode'),led)
  where
    mode' | key1R     = not mode
          | otherwise = mode

    led' = if mode then complement led else led

When building, the compiler keeps showing error

/home/jin/Lab4/de0/src/LED2.hs:31:16: error:
    • Unbound implicit parameters
        (ghc-prim-0.7.0:GHC.Classes.IP
           (Clash.Signal.HiddenClockName IntelSystem) (Clock IntelSystem),
         ghc-prim-0.7.0:GHC.Classes.IP
           (Clash.Signal.HiddenEnableName IntelSystem) (Enable IntelSystem),
         ghc-prim-0.7.0:GHC.Classes.IP
           (Clash.Signal.HiddenResetName IntelSystem) (Reset IntelSystem))
        arising from a use of ‘isRising’
    • In the expression: isRising 1 key1
      In an equation for ‘key1R’: key1R = isRising 1 key1
      In an equation for ‘topEntity’:
          topEntity clk rst key1
            = let
                (pllOut, pllStable)
                  = altpll @IntelSystem (SSymbol @"altpll50") clk rst
                rstSync
                  = resetSynchronizer pllOut (unsafeFromHighPolarity pllStable)
              in exposeClockResetEnable leds pllOut rstSync enableGen
            where
                leds = mealy ledT (1, False) key1R
                key1R = isRising 1 key1
   |
31 |       key1R  = isRising 1 key1

I have no idea what does this error mean. Even I modify the key1R = key1R = pure False, the error still exists:

/home/jin/Lab4/de0/src/LED2.hs:30:16: error:
    • Unbound implicit parameters
        (ghc-prim-0.7.0:GHC.Classes.IP
           (Clash.Signal.HiddenClockName IntelSystem) (Clock IntelSystem),
         ghc-prim-0.7.0:GHC.Classes.IP
           (Clash.Signal.HiddenEnableName IntelSystem) (Enable IntelSystem),
         ghc-prim-0.7.0:GHC.Classes.IP
           (Clash.Signal.HiddenResetName IntelSystem) (Reset IntelSystem))
        arising from a use of ‘mealy’
    • In the expression: mealy ledT (1, False) key1R
      In an equation for ‘leds’: leds = mealy ledT (1, False) key1R
      In an equation for ‘topEntity’:
          topEntity clk rst key1
            = let
                (pllOut, pllStable)
                  = altpll @IntelSystem (SSymbol @"altpll50") clk rst
                rstSync
                  = resetSynchronizer pllOut (unsafeFromHighPolarity pllStable)
              in exposeClockResetEnable leds pllOut rstSync enableGen
            where
                leds = mealy ledT (1, False) key1R
                key1R = pure False
   |
30 |       leds   = mealy ledT (1, False) key1R

UPDATE

By changing the topEntity from

topEntity clk rst key1 =
    let  (pllOut,pllStable) = altpll @IntelSystem (SSymbol @"altpll50") clk rst
         rstSync            = resetSynchronizer pllOut (unsafeFromHighPolarity pllStable)
    in   exposeClockResetEnable leds pllOut rstSync enableGen
    where
      leds   = mealy ledT (1, False) key1R
      key1R  = isRising 1 key1

to

topEntity clk rst key1 =
    let  (pllOut,pllStable) = altpll @IntelSystem (SSymbol @"altpll50") clk rst
         rstSync            = resetSynchronizer pllOut (unsafeFromHighPolarity pllStable)
    in   exposeClockResetEnable (mealy ledT (1, False) (isRising 1 key1)) pllOut rstSync enableGen

(basically just removing the where block), the code does compile now.