Does Verilator support SystemVerilog libraries?

Question

When compiling RTL from multiple sources it is normal to compile them into separate SystemVerilog libraries. Doing this means they cannot interfere with each other, and you can compile multiple different modules with the same name into different libraries.

SystemVerilog configurations are used to select which library to elaborate a module from. As described in the SV LRM 2017 (33 Configuring the contents of a design). E.g.

config cfg1; // specify rtl adder for top.a1, gate-level adder for top.a2
  design rtlLib.top;
  default liblist rtlLib;
  instance top.a2 liblist gateLib;
endconfig

Does Verilator support compilation into separate libraries like the commercial simulators?

Answer 1

No and it never will.

Chapter 33 of the LRM is specifically procluded from being supported by Verilator. See here: https://github.com/verilator/verilator/blob/master/docs/internals.rst#never-features