system-verilog - cross cover between generate-loop instances

Question

i would like to cross cover all fsm-states in all B instances. B instance number is controlled by a parameter that may change:

module A
...
  generate for (genvar i=0; i<PARAM; i=i+1)
    B #(..) B_inst (...)
...

module B
...
  logic [WIDTH-1:0] **fsm**;
...

what is the best way to write the cover-group for that case?