Error (10500): VHDL syntax error at sft.vhd(19) near text ":="; expecting ";"

Question

Please help me to find what is wrong in line 19

     library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sft is
    port(i : in std_logic_vector(2 downto 0) :="001" ;
    x : out std_logic_vector(2 downto 0));

end sft ;
architecture arc_sft of sft is
    begin
process_sft : process is 
            variable q : integer :=1 ;
            begin
                while q < 2 loop    
                    x <= std_logic_vector(unsigned(i) sll q) ;
                    q := q + 1;
            end loop ;
                  wait for q := 3 ;
                  end process process_sft ;
   end arc_sft ;`enter code here