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20
Devhide
2024-03-04T19:24:10.773000
58
Views
Set value of register to 64-bit integer in RISC-V
Published on
04 March 2024 at 19:24
#assembly
#cpu-architecture
#riscv
#instruction-set
37
Views
ARMv7A instruction
Published on
13 January 2024 at 20:08
#arm
#instruction-set
34
Views
Find common minimum CPU features to expect when targeting a certain macOS deployment target
Published on
09 January 2024 at 15:36
#macos
#cpu-architecture
#avx
#instruction-set
#avx2
107
Views
Why can't we do arithmetic on an operand in x86 asm?
Published on
30 December 2023 at 17:14
#assembly
#x86
#x86-64
#dereference
#instruction-set
98
Views
Arm cortex m0 LDR instruction
Published on
30 November 2023 at 11:12
#assembly
#arm
#cortex-m
#instruction-set
91
Views
Why is the "mov" with complex addressing faster than the corresponding "lea"?
Published on
23 November 2023 at 15:34
#assembly
#x86
#cpu-architecture
#instruction-set
78
Views
Jump (jmp) in microcode with fetch, decode, execute and writeback
Published on
18 November 2023 at 16:40
#assembly
#x86-16
#instruction-set
61
Views
How to decide minimum pmp region for an architecture?
Published on
15 November 2023 at 13:20
#operating-system
#cpu-architecture
#riscv
#instruction-set
#supervisor-mode
67
Views
Does RISCV SBI refers a hardware implementation or a software standard?
Published on
09 November 2023 at 06:54
#assembly
#cpu-architecture
#riscv
#instruction-set
#supervisor-mode
77
Views
In 6502 assembler, trying to output integers after log statement
Published on
25 October 2023 at 23:01
#assembly
#instruction-set
#6502
243
Views
How to compile for riscv zicond extension in gcc?
Published on
24 October 2023 at 07:56
#gcc
#riscv
#instruction-set
57
Views
Why there is different register address for sstatus an mstatus although they are different view of same register?
Published on
10 October 2023 at 14:02
#cpu-architecture
#privileges
#riscv
#instruction-set
91
Views
How data dependency handled at cpu instructions pipeline parallelism
Published on
07 October 2023 at 19:06
#parallel-processing
#x86
#cpu-architecture
#multicore
#instruction-set
141
Views
How does RESW in SIC machine works
Published on
16 September 2023 at 07:19
#assembly
#instruction-set
#microprocessors
#sic
123
Views
VM detection mechanisms for ARM
Published on
13 September 2023 at 03:50
#assembly
#arm
#virtual-machine
#cpu-architecture
#instruction-set
871
Views
Why is there "syscall" instruction in the x86-64 ISA, if syscalls are OS related?
Published on
16 August 2023 at 11:56
#assembly
#operating-system
#system-calls
#machine-code
#instruction-set
59
Views
ARMv8-a GNU assembler error : immediate out of range at operand 3
Published on
16 August 2023 at 07:52
#assembly
#arm64
#instruction-set
#armv8
#immediate-operand
113
Views
SIMD _mm_store_si128 | _mm_storeu_si128 don't storing correctly
Published on
11 August 2023 at 14:13
#c++
#simd
#intrinsics
#instruction-set
35
Views
Why mcyclecfg and minstretcfg is needed?
Published on
10 August 2023 at 14:27
#cpu-architecture
#privileges
#riscv
#perf
#instruction-set
302
Views
How does the control unit differentiate between Jr and the other R-type instructions if they have the same opCode?
Published on
08 July 2023 at 10:07
#mips
#cpu-architecture
#simulator
#instruction-set
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