How does a TLB manage memory translation for addresses that cross page boundaries?

Question

Let's say we have a page size of 4096 Bytes, and we have two contiguous virtual memory pages mapped to discontinuous physical pages, i.e

[x , x + 4096 * 2] - Maps to -> [A, A + 4096], [B, B + 4096]

x    x+4096  x+8192         A     A+4096   B     B+4096
|      |      |              |     |       |      |
|      |      |   --->       |     | ..... |      |
|      |      |              |     |       |      |

Let's say now we get an 8-byte memory access to address [x + 4090, x + 4098], which crosses page boundaries

x       x+4096   x+8192     
|  x+4090 |  x+4098 |
|     <---|--->     | 
|         |         |  

1. How is address translation handled in the TLB in such a scenario?
2. Is it handled in the TLB, or is the page boundary cross-detected prior to memory access in the CPU pipeline (maybe in the Load/Store Unit)?
3. How is such a situation handled in architectures which support multiple page sizes, 4K, 2M, 1G etc.