I am new to Vunit - but not testing. I currently have a setup where I have testbenches that use a lot of OSVVM where setup is provided via generics to the testbench, and I use either TCL or Pytest to run the test through a full test suite.
Having started looking into Vunit properly, I can see it might do what I'm after or at least allow me to move some of the test suit for some tests into the VHDL, but what I can't find is an example where part of the test case differences involve testing with different bus widths or sync/async clocks, for example.
Is there a way to do this via Vunit? if there is, is there an example I can look at? Or would you just expect to instantiate them all in the same Vunit testbench and run them in sequence?
My infrastructure is very OSVVM heavy, so I am not looking to change any of that - but I am looking for a runner to regress the testcases in GitLab. TCL doesn't cut it (mainly because ActiveHDL has a bug where it doesn't catch runtime exceptions properly in TCL).
VUnit has a configuration concept (not to be confused with VHDL configurations) that allow you to do that, among other things. You can read about it here.
You can also look at the following example.
I'm not sure if OSVVM heavy also implies using different VHDL configurations for different tests? If so, you should read this
Update based on comments:
Let's say we have a UUT with two generics, a
widththat can be 32/64/128 bits and a booleanuse_fifo. Here's a dummy (but executable) representation of that UUTAssume that we have a testbench and want to run that with all combinations of the generics. To do that we expose the UUT generics as generics to the VUnit testbench
Now we can create VUnit configurations for the testbench that represent all generic combinations. This is done in the run script.
If we list the tests we will see all six combinations: