LoanIO from HPS to FPGA get analog signals,cycloneVsoc dev kit,selfmade RTOS

Question

I’m working on a board that is a cycloneVsoc dev kit. The board has a simple RTOS program that I wrote.

Because the FPGA on the board does not have an external PIO interface, I used LoanIO to borrow the HPS GPIO interface (SPI CSn interface or MOSI/MISO interface) for the FPGA.

I hope that the GPIO borrowed by the FPGA can output a clock signal, which is implemented by a simple PLL on my FPGA. I did the connection and testing, and the signal was transmitted, but I observed that the signal from the GPIO output was an analog signal (3.3V * the duty cycle set by my PLL), but I still only want to get a digital signal.

I read the SPI interface protocol, and according to my understanding, these three channels should be digital signal channels. I suspect that my HPS settings changed them into analog signals, but I got nothing after reading the UG and RM.

This is my verilog FPGA code, it just simply connects the clock signal and the output port：

assign hps_h2f_loan_io_out[60] = clk_313; // clk_313 is a PLL output wire

The output voltage of LOANIO is 3.3V. When I change the duty cycle of the PLL clock, the output port of LOANIO changes accordingly: 50% -----> 1.62V, 75% -----> 2.43V, which basically matches the total voltage * duty cycle. Therefore, I infer that HPS converts the input digital signal into an analog signal.

If you have experience in this area of development or know the possible root cause of the problem, can you please help me solve it?

Answer 1

For those who use the same dev kit and have the same problem as mine,please do the following things to avoid this:

1. check the cycloneV soc address map reg: sysmgr.GENERALIOXX , sysmgr.LOANIOINXX and sysmgr.GPLMUXxx.

2. check the J31 jumper is shorted, so that SPI/I2C is set to SPI.

3.Ensure to set loanio.oe [xx] to desired input/output for FPGA logic, not HPS logic(although UG said otherwise)

4. Make sure your output bandwidth is below your main clk bandwidth, as the output increased to 1MHZ it started to loose the signal.(my mistake is that I added one more 0 to the output)

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