make Makefile, order of execution not behaving as expected with -include directive

Question

so I can find on the documentation of the make program that a Makefile is read from top to bottom... as should be a normal thing.

But I noticed when printing debug informations with make -nd these are the first lines of output:

GNU Make 4.3
Built for x86_64-pc-linux-gnu
Copyright (C) 1988-2020 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Reading makefiles...
Reading makefile 'Makefile'...
Reading makefile 'ctest1.d' (search path) (don't care) (no ~ expansion)...
Reading makefile 'ctest2.d' (search path) (don't care) (no ~ expansion)...
Updating makefiles....
 Considering target file 'ctest2.d'.
.... and so on...

This is the makefile, and if you watch the LAST line is an -include, in this include are stored the .d makefile.

#Disabling implicit rules
.SUFFIXES:

GCC := gcc
LDLIBS := -L./ -L/home/kevin/eclipse-workspace/CG/glfw/build/src
LDFLAGS := -lGL -lglfw3 -ldl -lX11 -lctest -lm -lpthread
CFLAGS := -I/home/kevin/eclipse-workspace/CG/include/ -I.
src := $(wildcard *.c)
obj := $(src:.c=.o)
headers := $(wildcard *.h)
deps := $(wildcard *.d)


# Specify how the object files should be created from the source files
main: $(obj)
    $(GCC)  $^ $(LDLIBS) $(LDFLAGS) -o $@

%.o : %.c 
    $(GCC) -c -g -Wall -MMD -o $@ $< $(CFLAGS) 

# Specify the target for cleaning up the project
.PHONY : clean
clean:
    rm -f $(obj) main $(deps) 

.PHONY : createDep
createDep:
    $(GCC) -E -MMD $(src) $(CFLAGS)
    
libctest.a: ctest1.o ctest2.o
    ar -cvq libctest.a ctest1.o ctest2.o
    
#ctest1.o: ctest1.c
#   gcc -c ctest1.c
    
#ctest2.o: ctest2.c
#   gcc -c ctest2.c

hi:
    echo $(src)
    echo $(headers)
    echo $(deps)


test: utils.o
    gcc $< -o $@

-include $(deps)

So... how can the LAST line be executed for first?

Thx regards

I expect the debugging output to show sequentially what is written in the Makefile.

Answer 1

See the GNU Make Manual: 3.7 How make Reads a Makefile, particularly the first paragraph:

GNU make does its work in two distinct phases. During the first phase it reads all the makefiles, included makefiles, etc. and internalizes all the variables and their values and implicit and explicit rules, and builds a dependency graph of all the targets and their prerequisites. During the second phase, make uses this internalized data to determine which targets need to be updated and run the recipes necessary to update them.

This can be summarized roughly as: First, GNU make reads all the makefiles, including the -include-ed makefiles. After that, it starts to make or update the targets that need to made updated. So in the output you have quoted, this is the first phase:

Reading makefiles...
Reading makefile 'Makefile'...
Reading makefile 'ctest1.d' (search path) (don't care) (no ~ expansion)...
Reading makefile 'ctest2.d' (search path) (don't care) (no ~ expansion)...

The top-level makefile Makefile is read; then the first -include-ed makefile ctest1.d, and finally the second -include-ed makefile ctest2.d. As you see, Makefile is read from top to bottom.

And this is the second phase, where make starts making and updating targets (beginning with updating any makefiles that need updated):

Updating makefiles....
 Considering target file 'ctest2.d'.
... [cut]...