MyHDL Signals inside functions not showing up in VCD

Question

Should I be able to see these in the generated VCD file?

   @always(clk.posedge)
    def MentorCluster():
        j = Signal(0)
        mentorq0, mentorq1, mentorq2, mentorq3 = [[Signal(0) for j in range(10)] for i in range(4)]

I can see all the signals I created at the top level, but not the ones local to the function

Here is the code I used to generate the VCD:

def simulate(timesteps):
    traceSignals.timescale = "1ps"
    tb = traceSignals(avaca)
    sim = Simulation(tb)
    sim.run(timesteps)
    sim.quit()

#simulate for 2000 ticks (picoseconds) -- very ambitious to do all this in 2ns!
simulate(2000)

Answer 1

Signals created inside an `always’ will not only not show up in the .vcd, but also won’t work. Here is a small test program to try this.

'''

                   delay, StopSimulation)


@block
def f1(clk, sigin, sigout):
    # this is the place to declare Signals and ListOfSignals
    sigind1 = Signal(intbv(0)[4:])
    mentorq0, mentorq1, mentorq2, mentorq3 = [[Signal(bool(0)) for j in range(10)] for i in range(4)]

    @always_seq(clk.posedge, reset=None)
    def f1s():
        # declaring Signals and ListOfSignals won't work
        # sigind1 = Signal(intbv(0)[4:])
        # mentorq0, mentorq1, mentorq2, mentorq3 = [[Signal(bool(0)) for j in range(10)] for i in range(4)]

        sigind1.next = sigin
        mentorq0[0].next = sigind1[0]
        mentorq1[0].next = sigind1[1]
        mentorq2[0].next = sigind1[2]
        mentorq3[0].next = sigind1[3]
        for i in range(1, 10):
            mentorq0[i].next = mentorq0[i - 1]
            mentorq1[i].next = mentorq1[i - 1]
            mentorq2[i].next = mentorq2[i - 1]
            mentorq3[i].next = mentorq3[i - 1]
        sigout.next[0] = mentorq0[9]
        sigout.next[1] = mentorq1[9]
        sigout.next[2] = mentorq2[9]
        sigout.next[3] = mentorq3[9]

    return f1s


if __name__ == '__main__':
    import random
    random.seed = 'We want repeatable randomness'

    @block
    def tb_f1():
        clk = Signal(bool(0))
        sigin = Signal(intbv(0)[4:])
        sigout = Signal(intbv(0)[4:])

        tCK = 10

        dut = f1(clk, sigin, sigout)

        @instance
        def genclk():
            while True:
                clk.next = not clk
                yield delay(int(tCK // 2))

        @instance
        def stimulus():
            yield delay(int(tCK * 3.5))
            for __ in range(10):
                sigin.next = random.randint(1, 15)
                yield delay(tCK)
            yield delay(tCK * 20)

            raise StopSimulation

        return instances()

        # finally
    dft = tb_f1()
    dft.config_sim(trace=True)
    dft.run_sim()

When we activate the Signals inside the always block sigout will remain 0