Non-synthesizable clocking style: only conditional operations or if statements are supported in sync-async always blocks

Question

I am trying SV code which involves both using priority and casez constructs together. What I want to achieve is based on the valid request available (sel is a 4-bit register which will contain who has valid request at a time). An output will be generated based on the least significant bit who has valid request.

always @ (posedge clk or negedge rst) 
begin 
Priority casez(sel) 
4'b0000: check = 4'b0;
4'b???1: check = 4'b1;
4'b??1?: check = 4'b2;
4'b?1??: check = 4'b4;
4'b1???: check = 4'b8;
default: check = 4'b0;
endcase
end

When I try to execute this code through emulation, I am facing an issue which states:

Non-synthesizable clocking style: only conditional operations or if statements are supported in sync-async always blocks

Does this mean that priority casez can't be synthesized? If it's not possible, what's the best way to achieve this without defining each and every possible combination of sel?

Answer 1

Since you have rst in the sensitivity list, you must also use it in the body of the always block. For example, if you want an asynchronous reset, you would add an if/else statement:

always @ (posedge clk or negedge rst) begin
    if (!rst) begin
        check <= 4'd0;
    else begin
        priority casez (sel) 
            4'b0000: check <= 4'd0;
            4'b???1: check <= 4'd1;
            4'b??1?: check <= 4'd2;
            4'b?1??: check <= 4'd4;
            4'b1???: check <= 4'd8;
            default: check <= 4'd0;
        endcase
    end
end

I corrected some syntax errors. The priority keyword must be lower case. It is illegal to use the 'b base specifier with numbers like 2, 4 and 8. I changed the specifier to 'd.

Also, good coding practices recommend using nonblocking assignments (<=) for sequential logic.