I found a piece of watchdog driver code for an i.MX RT 1xxx Arm-Cortex M7, before initializing the WDT, there was an Icache disable, and an enable just after the WDT initialization. Does anyone know why is that done and if is it necessary?
Nothing was tried, just want to understand why the instruction cache is disabled to initialize the watchdog.
You may find this PDF helpful to understand the L1 caches of the i.MX RT processors.
https://drive.google.com/file/d/1-xxoxiAE0Znfn5awpJt2BE9T7Y8p-Wbv/view?usp=sharing