The interesting observation I made recently while using GCC to compile for a Cortex M0 is that the veneer code generated in my project appears to be aligned to 8-byte boundaries.
Slightly modify the function before the veneer code:
Did you notice? In addition to the added NOP instructions, the compiler generated an additional 3 padding data, thereby pushing the veneer code to the next 8-byte aligned address. I searched the ARM official website for information about veneer, but did not find any evidence related to this.
BTW, in my linker script, no special treatment is given to the veneer code, and all handling related to veneer code is done by the compiler and linker.
How does this happen? Does anyone know the reason? Thank you.