RISC-V paging: what decides the way the Dirty and Accessed bits are managed?

Question

RISC-V privileged ISA specification section 4.3.1 ("Addressing and memory protection") says that two schemes of managing the Dirty and Accessed bits on the leaf pages are permitted:

• Either the implementation makes a page fault when accessing/writing a page without the corresponding bit set (so that the page fault handler can "fix" that),
• or the bits are managed and set automatically by the hart implementation (w.r.t. some assertions about memory order).

From the point of view of OS implementor, who decides which scheme of these should I use (and rely on)? More particularly, how do I find that the dirty bits are able to "manage themselves" and I don't need to do anything, or that I have to supply the functionality in the page fault handler?

I did not spot any such info in the spec; so hoping there is a notice somewhere that clarifies it, or perhaps a safe way to fallback in both schemes.

Answer 1

After consulting the #riscv IRC channel, I got an answer from <geist> (thanks!):

There are extensions Svade (previously Ssptead) and Svadu that set the behavior properly and can be checked from the ISA string.

As I understand it, the behavior is completely unspecified if none of the extensions are present.

Details are available at the extension site at https://github.com/riscv/riscv-svadu and in the profile listing at https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc .