Sunxi ARM SoC wake-up cause?

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I'd like to capture the wake-up reason using ATF (Trusted Framework A) specifically for sun50i, but applicable to many sunxi SoCs.

Since an IRQ or NMI likely wakes up the SoC, an interrupt flag would be set. I figure the following code will help identify the IRQ, but I don't where in the wake-up flow to install this code.

#define mmio_read_32(c)      ({unsigned int __v = (*(volatile unsigned int *)(c)); __v; })
#define GICC_BASE            0x01c82000

INFO("SGI 0:       0x%04x\n",      mmio_read_32(GICC_BASE + 0x0000));
INFO("PPI 0:       0x%04x\n",      mmio_read_32(GICC_BASE + 0x0040));
INFO("UART 0:      0x%04x\n",      mmio_read_32(GICC_BASE + 0x0080));
INFO("TWI 0:       0x%04x\n",      mmio_read_32(GICC_BASE + 0x0098));
...
INFO("DE:          0x%04x\n",      mmio_read_32(GICC_BASE + 0x01fc));
INFO("CTI0:        0x%04x\n",      mmio_read_32(GICC_BASE + 0x0230));
INFO("PMU0:        0x%04x\n",      mmio_read_32(GICC_BASE + 0x0260));
INFO("PMU1:        0x%04x\n",      mmio_read_32(GICC_BASE + 0x0264));
INFO("PMU2:        0x%04x\n",      mmio_read_32(GICC_BASE + 0x0268));
INFO("PMU3:        0x%04x\n",      mmio_read_32(GICC_BASE + 0x026c));
INFO("AXI_ERROR:   0x%04x\n",      mmio_read_32(GICC_BASE + 0x0270));

There is a register that survives a reset: "General Purpose Register can be flag register, and it will save the value all the time when the VDD_RTC is not power off", but the problem remains on how to ascertain the wake-up reason.

Ref: Allwinner A64 user manual


The above code comes from hints from the Allwinner A64 user manual.

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