Verilog Implementation: Detecting Overflow and Rolling Up Result

Question

`Hey everyone, I'm working on a Verilog project and need some guidance on implementing overflow detection and rolling up the result. Here's what I'm trying to achieve:

I have a 32-bit addition operation in Verilog, and I want to detect if overflow occurs during the addition process. Specifically, I'm looking to detect if the carry out of the current addition operation (cn​) XOR with the carry out from the previous addition operation (cn−1​) indicates an overflow condition. If overflow is detected, I'd like to roll up the result.

Could someone provide insights or a sample Verilog code snippet on how to implement this overflow detection and result roll-up mechanism in Verilog?

Thanks in advance for any help or suggestions!`

module CSelA32 (
output [31:0] sum,
output cout,
output overflow,
input [31:0] a,
input [31:0] b
);
wire [31:0] sum0, sum1;
wire [6:0] c;
wire [6:0] cout0, cout1;
wire overflow_next;
RCA4 rca0_0 ( .sum(sum[3:0]), .cout(c[0]), .a(a[3:0]), .b(b[3:0]), .cin(1'b0) );
  RCA4 rca_other_0[6:1](.sum(sum0[27:4]), .cout(cout0[5:0]), .a(a[27:4]), .b(b[27:4]), .cin(1'b0));
  RCA4 rca_other_1[6:1](.sum(sum1[27:4]), .cout(cout1[5:0]), .a(a[27:4]), .b(b[27:4]), .cin(1'b1));
  MUX2to1_w4 mux_other_sum[6:1](.y(sum[27:4]), .i0(sum0[27:4]), .i1(sum1[27:4]), .s(c[5:0]));
  MUX2to1_w1 mux_other_cout[6:1](.y(c[6:1]), .i0(cout0[5:0]), .i1(cout1[5:0]), .s(c[5:0]));
RCA4 rca7_0 (.sum(sum0[31:28]), .cout(cout0[6]), .a(a[31:28]), .b(b[31:28]), .cin(1'b0) );
RCA4 rca7_1 ( .sum(sum1[31:28]), .cout(cout1[6]), .a(a[23:20]), .b(b[23:20]), .cin(1'b1) );
MUX2to1_w4 mux6543210_sum ( .y (sum[31:28]), .i0(sum0[31:28]), .i1(sum1[31:28]), .s (c[6]) );
MUX2to1_w1 mux6543210_cout ( .y (cout), .i0(cout0[6]), .i1(cout1[6]), .s (c[6]) );
endmodule