Verilog Mixed bool and bit operator

Question

What will this construct do in verilog?

z= a && (b[1:0]=0) && c

where

a:wire

c:[3:0] wire

z:[3:0] wire

Looks like a mixup of bool and bitwise OPs?

Answer 1

As dave_59 mentioned you have a syntax error in your code. Assuming you meant z = a && (b[1:0] == 0) && c that would be equivalent to z = a && (b[1:0] == 0) && |c. That means z=0001 if a is 1 and all b bits are 0 and at least one of the c's bits is 1. Otherwise z=0000.

Following I create the module along with its test bench, printing truth table for the module. Hope it's useful.

module stackoverflow_78202191(a, b, c, z);
  input a;
  input [1:0] b;
  input [3:0] c;

  output [3:0] z;
  
  assign z = a && (b[1:0] == 0) && c;
    
endmodule

module stackoverflow_78202191_tb();

  reg a;
  reg [1:0] b;
  reg [3:0] c;
  wire [3:0] z;

  stackoverflow_78202191 uut (
    .a(a),
    .b(b),
    .c(c),
    .z(z)
  );

  initial begin
    a = 0;
    repeat(4) #128 a = ~a;
  end

  initial begin
    b = 2'b00;
    repeat(8 * 2) #32 b = b + 1;
  end

  initial begin
    c = 4'b0000;
    repeat(128 * 2) #2 c = c + 1;
  end

  initial
    begin
      #1;
      repeat(128 * 2) #2 $display("uut(%b, %b, %b) = %b", a, b, c, z);
      $finish ;
    end

endmodule