verilog occur the error of "expecting a statement [9(IEEE)]"

Question

Recently I am doing verilog program about FSM. Two sequences of positive integers will be sequentially loaded into the circuit, one pair of integers per cycle. The length of a sequence (the number of the integers in a sequence) is not a fixed value. The two “valid” integers which are loaded into the circuit in a cycle will perform an operation and generate a result. After loading two sequences entirely, there should be many results. The circuit needs to find the maximum among these results and output it (the maximum).

However, I have tried many times and the program still cannot work. Can somebody help me to find the problem and fix it?

        else
           |
xmvlog: *E,NOTSTT (111022203_2.v,42|11): expecting a statement [9(IEEE)].
    module worklib.find_MAX:v
        errors: 1, warnings: 0
    module worklib.FSM:v
        errors: 0, warnings: 0
    module worklib.decide_max:v
        errors: 0, warnings: 0
xmverilog: *E,VLGERR: An error occurred during parsing.  Review the log file for errors with the code *E and fix those identified problems to proceed.  Exiting with code (status 1).

`timescale 1ns/1ps
module find_MAX(
    input wire clk,
    input wire rst_n,
    input wire start,
    input wire valid,
    input wire [7:0] Data_A,
    input wire [7:0] Data_B,
    input wire one_left,
    input wire [2:0] instruction,
    output reg [7:0] maximum,
    output reg finish
);
    wire [7:0] result;

    // Functional_Unit instantiation
    Functional_Unit fu(
        .instruction(instruction),
        .A(Data_A),
        .B(Data_B),
        .F(result)
    );

    //TODO: write your design below
    //You cannot modify anything above

    wire [1:0] state;
    wire o_finish;
    wire [7:0] o_maximum;

    assign o_maximum = 8'b0;
    assign o_finish = 0;

    FSM M1 (clk, rst_n, state, valid, start, one_left, o_finish);

    decide_max M2 (result, valid, state, maximum, o_maximum);

    always @(posedge clk) begin
        if (~rst_n)
            maximum <= 8'b0;
            finish <= 0;
        else
            maximum <= o_maximum;
            finish <= o_finish;
    end

endmodule

I've modified the always block in find_MAX block or initialize the value of maximum and finish but still fail to operate it.

Answer 1

If your if clause contains multiple statements, you must use begin/end:

    always @(posedge clk) begin
        if (~rst_n)
          begin
            maximum <= 8'b0;
            finish <= 0;
          end
        else
          begin
            maximum <= o_maximum;
            finish <= o_finish;
          end
    end