In AMD's optimization manual, the L1 Data cache is described as follows:
The L1 DC provides multiple access ports using a banked structure. The read ports are shared by three load pipes and victim reads. Store commits utilize separate write ports. Which DC banks are accessed is determined by address bits 5:3 by the access, the size of the access, and the DC way. DC way is determined using the linear-address-based utag/way-predictor
What does the bank here mean in terms of hardware? What is the relationship between it and the logical set/way of cache?
Is the bank designed similarly to memory bank?