Thanks for pondering over my question.
Above is a digital logic circuit with 2 inputs, & 1 output. I want following logic to be implemented in sequence :
- b = 0, a = 0, Y = 0
- b = 1, a = 0, Y = 1
- b = 0, a = 1, Y = 1
- b = 1, a = 1 should be explicitly avoided so that both a & b are not 1 simultaneously
- Suppose step 3 is tried before step 2, then output should be 0, i.e., Y = 0.
Which logic gate or digital circuit will work for above sequence of logical ops ? I tried with OR and XOR gates, but they don't satisfy condition 5, and sequential operation can't be enforced.
Can I use 2-to-1 priority encoder such as the one shown in figure below ?

Or may be some smart implementation of NOR SR latch ? Please let me know of your thoughts. Thanks ahead of the time.

f XOR aseems to fit perfectly.How is it that you feel it contradicts condition 1?