Let's say I want to add 4 binary numbers in 2's Complement: a+b+c+d. I have a circuit that can add 2 binary numbers at a time, and that detects whether overflow has occurred for the corresponding sum (by using XOR with the last carry bits).
When adding multiple numbers in 2's Complement, it is possible that the intermediate sums overflow, while the final result does not. For example:
4 + 5 + (-6) expressed with 4 bits and C2:
0100 +
0101
====
1001 (-7 : overflow)
1001 +
1010
====
0011 (3, the correct result)
My question is: how can I know, when adding 4 binary numbers with N bits, whether the final result overflows or not? Is there any logical expression or circuit that can automatically detect when overflow occurs?
In your example, 0100 + 0101, represented with 4 bits, gives the hardware result of 1001.
It is now up to you how you interpret these bits.
If you interpret them as 2’s complement integers, the result is wrong (decimal -7, overflow).
If you interpret them as unsigned integers, the result is correct (decimal 9).
If you add then 1010, you have to think about how to interpret these bits. Unsigned, they are decimal 10, 2’s complement, they are decimal -6.
Still, it is up to you, how you interpret the result. It is 0011 plus a carry bit, since 1001 + 1010 gives 10011.
Thus the problem arises because you change the interpretation of the bits during the computation.
This cannot be handled by any logical expression or circuit.