Why does the V flag shown in the addition in assembly language below is set to 1 instead of 0? Why does the overflow occur?

Question

Here is a question on a practice quiz that I did but I do not understand why the V flag is 1.

Answer 1

$83 = –125
$74 = 116

–125 – 116 = –241, which doesn’t fit in 8 bits. (The range of an 8-bit signed number is –128 to +127.) Since the result doesn’t fit, you get signed overflow, which sets the V bit.

Answer 2

$83 - $74 = $83 + (-$74) = $83 + (~$74) + 1

This is how the logic sees it.

          1
   10000011
+  10001011
==============

finish

  100000111
   10000011
+  10001011
==============
   00001111

Two equivalent ways to determine the v flag if the carry in and the carry out of the msbit don't match then the v flag is set else not set. The other way is if the msbits of the operands (remember to invert and add one since this is addition in logic not subtraction) are the same and the result msbit is different than the two matching operands then it is an overflow otherwise if all three are the same or the two operand msbits differ then v = 0.

This is the how, to understand the why see prl's answer, the answer does not fit in the number of bits available.

The C flag is specific to architecture to do a subtract you invert the second operand and invert the carry in (make it a 1) on the way in, on the way out some architectures invert the carry out making it a borrow bit, others leave it as is. Often not documented, so you have to experiment to find out what the architecture does.