I would like to write verilog that can be synthesized either using yosys (preferable) or the Lattice Radiant tool chain using Synplify (needed for encrypted IP from Lattice for example).
Most of the hard cells like the PLL have different names between the two tools.
Is there a verilog library that allows one to choose either synthesis tool with a single 'define for example?
Yosys and Synplify compatible elements
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Unfortunately not, the open source iCE40 flow was developed before Radiant existed; so used the original iCEcube primitive library (which is still the only option for devices pre-UltraPlus). For reference this is documented at http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf - imo it is Lattice who are at fault for failing to provide backwards compatibility with their own library...