I am trying to construct a procedure for my testbench that each clock cycle reads data from an external FIFO and insert the data into an internal array in the testbench.
My objective is for the procedure to read data from the FIFO until it is empty. The problem I am having is that it appears to only read one word before exiting the procedure.
procedure read_uplink_FIFO(
signal clk : in std_logic;
)is
variable rd_cnt : integer := 0;
begin
if rising_edge(clk) then
if fifo_empty_o = '0' then
rd_ena_i <= '1';
uplink_fifo_reg(rd_cnt) <= rd_data_o;
rd_cnt := rd_cnt + 1;
elsif fifo_empty_o = '1' then
rd_ena_i <= '0';
rd_cnt := 0;
end if;
end if;
end;
The procedure is called inside the testbench main process, after write operations to the FIFO is known to be complete:
wait until rising_edge(clk);
read_uplink_FIFO(clk);
I do not have much experience with procedures, and information concering my problem is limited. I am wondering if I am using the procedure wrong or if it is even possible to use a procedure for my objective.
I tried to switch around the nested if statement without any success:
if fifo_empty_o = '0' then
if rising_edge(clk) then
...
end if;
elsif fifo_empty_o = '1' then
.....
This being a testbench, you can create a procedure that simply loops a number of times until the fifo is empty. A procedure along those lines would look something like this:
This is just an example. Please tailor to your own needs.