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Need clarification on VHDL expressions involving std_logic_vector, unsigned and literals, unsure about compiler interpretation

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#math #types #vhdl #unsigned #ieee
46
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uart in vhdl send a string

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#vhdl #fpga #uart
39
Views

How do I diagnose and fix COMP96 ERROR COMP96_0055 and COMP96 ERROR COMP96_0056 when using Vunit to run my VHDL test bench

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#vhdl #active-hdl #vunit
83
Views

VHDL Finite State Machine not transitioning correctly based on external signal

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#vhdl #simulation #fsm
37
Views

Binary Coded Decimal Counter in VHDL

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#vhdl #counter #bcd
48
Views

My VHDL ALU code fails to output the result of addition, but outputs the result of subtraction just fine?

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#vhdl #ghdl
52
Views

Padding zeros with std_logic_vector results in Implementation Error

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#vhdl #fpga #vivado
32
Views

What is the order of porches, visible video data, and sync periods in HDMI protocol?

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#vhdl #hdmi
39
Views

Im trying to buil a “N” bit parameterizable accumulator based in an adder and in a register, both parameterizable

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#vhdl #quartus
49
Views

Simulation of a register and an incrementer with VHDL

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#vhdl
57
Views

VHDL Error - Washing Machine - unresolved signal is multiply driven

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#vhdl #project #xilinx #vivado #vivado-hls
62
Views

Traffic light junction in VHDL

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#vhdl
63
Views

Addition of one 4-bit and one 3-bit inputs in VHDL

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#resize #vhdl #alu
68
Views

4 input nand gate using 2 input nand

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#vhdl
65
Views

how to implement a Vhdl code for 2bit karatsuba algorithm

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#vhdl #xilinx #karatsuba
59
Views

VHDL/GHDL: Why does port name hide entity?

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#warnings #vhdl #ghdl
65
Views

How can I avoid glitches in behavioural vhdl code simulations?

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#vhdl #modelsim #digital #digital-design
80
Views

VHDL Vivado: Can I make a variable std_logic_vector from separate std_logic inputs in the test bench?

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#vhdl #vivado
62
Views

VHDL: using rising_edge with normal signals

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#vhdl #fpga #clock
125
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Why would a simulation/synthesis mismatch occur with non-blocking initialization of signals?

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#verilog #vhdl #system-verilog

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