Padding zeros with std_logic_vector results in Implementation Error

Question

I'm encountering an issue with Vivado where zero-padding in my VHDL code is not being preserved in the elaborated design and results in Implementation Error. Here's a brief overview of the problem:

I have a 14-bit counter in my VHDL design, and I need to concatenate it with zeros to form a 32-bit signal before assigning it to a RAM input. I achieved this using the following code snippet:

ram_input <= "000000000000000000" & i;

Here is the elaborated design snapshot, where zeros are missing to make ram_input 32-bit wide, it just take counter i (14-bits) value

In simulation, everything works as expected, and the counter value is correctly padded with zeros. However, in the elaborated design generated by Vivado, only the 14 bits of the counter seem to be considered, disregarding the zero-padding.

Has anyone else encountered a similar issue with Vivado or other synthesis tools? Are there any specific settings or techniques I should be aware of to ensure that zero-padding is preserved in the elaborated design?

Any insights or suggestions would be greatly appreciated.

Thank you in advance for your help!

I want to expect suggested way to append zeros with i (std_logic_vector) to make it 32-bit wide and could see the block in Elaborated Design. Now, it just take counter i value as an Input.