GCC generates SIMD and FP instructions for Cortex-A53 without NEON

Question

I compile my C code with aarch64-none-elf-gcc and I add option -mcpu=cortex-a53+nofp. However it seems that the "+nofp" doesn't work and I still get FP instructions (3d8047e0). Could anyone help me to solve this?

Disassembly of section .text.snprintf:

00000042000014d0 <snprintf>:
  42000014d0:   a9a47bfd    stp x29, x30, [sp, #-448]!
  42000014d4:   900002e9    adrp    x9, 420005d000 <strlen+0xc0>
  42000014d8:   b2407be8    orr x8, xzr, #0x7fffffff
  42000014dc:   910003fd    add x29, sp, #0x0
  42000014e0:   f9000bf3    str x19, [sp, #16]
  42000014e4:   3d8047e0    str q0, [sp, #272]

null.......................

Answer 1

Cortex a53 is an armv8 -processor, which does have ASIMD aka NEON instruction set as mandatory. q0 is a generic register that can hold and operate on both integer and fp data; this instruction does not imply that the content is floating point.