Question

My VHDL ALU code fails to output the result of addition, but outputs the result of subtraction just fine?

score 48 · Answer 1 · 2024-03-25T16:09:56.307000

48

Views

My VHDL ALU code fails to output the result of addition, but outputs the result of subtraction just fine?

Published on 25 March 2024 at 16:09

score 59 · Answer 2 · 2024-03-02T11:47:28.533000

59

Views

VHDL/GHDL: Why does port name hide entity?

Published on 02 March 2024 at 11:47

score 66 · Answer 3 · 2024-01-27T15:05:40.877000

66

Views

VHDL program's (Design+Testbench) run time is 0 sec

Published on 27 January 2024 at 15:05

score 158 · Answer 4 · 2023-11-05T10:59:13.947000

158

Views

VHDL when running ghdl -r my testbench is getting stuck after passing two values

Published on 05 November 2023 at 10:59

score 97 · Answer 5 · 2023-08-21T13:15:35.340000

97

Views

GHDL cannot find function defined in package

Published on 21 August 2023 at 13:15

score 230 · Answer 6 · 2023-07-11T18:34:12.680000

230

Views

Could not find gnatmake binary after MacOS installation

Published on 11 July 2023 at 18:34

score 651 · Answer 7 · 2022-11-03T15:52:49.780000

651

Views

vhdl: Why is aggregate assignment not allowed in this context?

Published on 03 November 2022 at 15:52

score 221 · Answer 8 · 2022-10-26T14:06:51.667000

221

Views

VHDL: Mealy FSM not producing state changes at clock edges?

Published on 26 October 2022 at 14:06

score 89 · Answer 9 · 2022-08-27T09:42:23.793000

89

Views

VHDL declaration expression cannot contain relational operator?

Published on 27 August 2022 at 09:42

score 401 · Answer 10 · 2022-05-25T02:40:01.217000

401

Views

Redirecting output of tcl proc to file and output (like tee) Part 2

Published on 25 May 2022 at 02:40

score 122 · Answer 11 · 2022-04-15T03:17:16.023000

122

Views

Unable to output data entered into a register

Published on 15 April 2022 at 03:17

score 551 · Answer 12 · 2022-03-08T17:41:09.963000

551

Views

Using Unisim with GHDL: vital_timing and vital_primitives not found in ieee library

Published on 08 March 2022 at 17:41

score 313 · Answer 13 · 2022-03-02T23:29:20.300000

313

Views

Unable to output data from ram memory address

Published on 02 March 2022 at 23:29

score 374 · Answer 14 · 2022-01-18T18:15:32.157000

374

Views

space is required between number and unit name

Published on 18 January 2022 at 18:15

score 206 · Answer 15 · 2022-01-11T18:30:54.540000

206

Views

ghdl never terminates and I don't know, why

Published on 11 January 2022 at 18:30

score 160 · Answer 16 · 2022-01-02T16:27:49.773000

160

Views

Unable to synthesize code. GHDL throws an array bounds error

Published on 02 January 2022 at 16:27

score 340 · Answer 17 · 2021-12-11T19:36:03.023000

340

Views

VHDL AND operator usage " no function declarations for operator "and""

Published on 11 December 2021 at 19:36

score 282 · Answer 18 · 2021-09-16T10:52:35.700000

282

Views

purpose of command in makefile

Published on 16 September 2021 at 10:52

score 768 · Answer 19 · 2021-07-10T17:51:49.727000

768

Views

GHDL -fsynopsys and -fexplicit options

Published on 10 July 2021 at 17:51

score 197 · Answer 20 · 2021-06-04T21:31:41.817000

197

Views

error running ghdl sample dlx implementation

Published on 04 June 2021 at 21:31

List Question

My VHDL ALU code fails to output the result of addition, but outputs the result of subtraction just fine?

VHDL/GHDL: Why does port name hide entity?

VHDL program's (Design+Testbench) run time is 0 sec

VHDL when running ghdl -r my testbench is getting stuck after passing two values

GHDL cannot find function defined in package

Could not find gnatmake binary after MacOS installation

vhdl: Why is aggregate assignment not allowed in this context?

VHDL: Mealy FSM not producing state changes at clock edges?

VHDL declaration expression cannot contain relational operator?

Redirecting output of tcl proc to file and output (like tee) Part 2

Unable to output data entered into a register

Using Unisim with GHDL: vital_timing and vital_primitives not found in ieee library

Unable to output data from ram memory address

space is required between number and unit name

ghdl never terminates and I don't know, why

Unable to synthesize code. GHDL throws an array bounds error

VHDL AND operator usage " no function declarations for operator "and""

purpose of command in makefile

GHDL -fsynopsys and -fexplicit options

error running ghdl sample dlx implementation

Trending Questions

Popular # Hahtags

Popular Questions