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633
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$dumpfile and $dumpvars not working in vscode error in terminal says requires system verilog

Published on
#verilog #system-verilog #iverilog #icarus
285
Views

localparam / parameter with unpack array : icarus

Published on
#verilog #system-verilog #iverilog #icarus
108
Views

reg qb; cannot be driven by primitives or continuous assignment

Published on
#verilog #hdl #iverilog #icarus
268
Views

Ring oscillator in Verilog/SystemVerilog - supressing undefined states

Published on
#undefined #verilog #system-verilog #icarus
241
Views

When simulating verilog output using Icarus, is there a way to include FPGA hardware features such as RAM in the simulation?

Published on
#simulation #fpga #icarus
542
Views

Testing multiple configurations of parameterizable modules in a Verilog testbench

Published on
#verilog #system-verilog #test-bench #icarus
95
Views

Verilog module not being called

Published on
#verilog #icarus
251
Views

Washing Machine in Verilog

Published on
#verilog #system-verilog #icarus
2.7k
Views

Error opening .vcd file. No such file or directory

Published on
#verilog #icarus #gtkwave
319
Views

Why isn't ModelSIM displaying timing waveforms, whereas GTKWave does?

Published on
#verilog #modelsim #icarus #gtkwave
143
Views

Behavioral Modeling is not a valid l-value in testbench.test

Published on
#verilog #hdl #icarus
626
Views

Why the memory content is not read? - verilog digital system design

Published on
#memory #verilog #system #digital #icarus
1k
Views

How to test if a 3-bit bus has the first bit set on 1 - verilog

Published on
#testing #verilog #bus #icarus
220
Views

I see undefined output sequences reading a memory in simulation

Published on
#memory #verilog #simulate #test-bench #icarus
232
Views

I cannot see the contents of a memory

Published on
#memory #verilog #simulation #instantiation #icarus
152
Views

Can't see anything when accessing RAM contents in simulation

Published on
#memory #verilog #simulation #hdl #icarus
458
Views

Cannot load/store data from/in SRAM: read data is unknown

Published on
#memory #verilog #icarus
958
Views

Can't create a 'real' type array in Verilog

Published on
#arrays #parameters #verilog #icarus
606
Views

why are icarus verilog specify times not respected?

Published on
#verilog #system-verilog #icarus
336
Views

How to know which simulator is used in cocotb testbench?

Published on
#python #verilog #icarus #cocotb #verilator

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