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20
46
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uart in vhdl send a string

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#vhdl #fpga #uart
33
Views

A FPGA Project Proposal where I can use both PS and PL

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#embedded #fpga #vivado #hdmi #soc
55
Views

IO placement is infeasible error in Vivado

Published on
#constraints #verilog #fpga #vivado
41
Views

Why RTOS is needed for FPGA based real-time embedded system?

Published on
#embedded #real-time #fpga #rtos
52
Views

Padding zeros with std_logic_vector results in Implementation Error

Published on
#vhdl #fpga #vivado
100
Views

How to write into 12 addresses at the same cycle in vivado and still be recognized as BRAM

Published on
#verilog #system-verilog #fpga #vivado
12
Views

PLL not showing output on ModelSim

Published on
#fpga #modelsim #lattice-diamond
26
Views

Using FPGA to sample and filter audio based off switch selection

Published on
#c #fpga #texas-instruments
29
Views

Why is there no output from the verilog test bench?

Published on
#unit-testing #verilog #fpga
14
Views

Freeze after two subsequent software resets for Zynq 7000 FPGA (with SoC)

Published on
#fpga #reset #watchdog #zynq
43
Views

Verilog module always going to default case when assigning value to input

Published on
#verilog #fpga #quartus #intel-fpga #questasim
16
Views

Where do I find the Xilinx xc7z007sclg400-1 master constaint file?

Published on
#fpga #xilinx
78
Views

Failed to use memory bits in fpga

Published on
#memory #verilog #fpga #ram #quartus
28
Views

How to increase baudrate on Device Manager Windows?

Published on
#windows #serial-port #fpga #uart #com-port
48
Views

Gate-Level Sim: Hold time violation between testbench and first registers?

Published on
#verilog #system-verilog #fpga #asic
43
Views

Can SYSCLK be included in FPGA Xilinx vivado testbenches?

Published on
#fpga #clock #xilinx #vivado #test-bench
48
Views

Are FPGA GPIOs capable enough to read bits at a high rate (26Mbps)? If not, what is a possible way?

Published on
#emulation #fpga #gpio #xilinx #vlsi
20
Views

Install SoC EDS and create .o file using Cygwin

Published on
#cygwin #fpga #quartus #soc
39
Views

u-boot stuck at starting kernel for zybo z7

Published on
#fpga #xilinx #u-boot #l4re
46
Views

Optimizing Gaussian Elimination using High Level Synthesis

Published on
#c++ #parallel-processing #fpga #pragma #vivado-hls

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