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List Question
20
Devhide
2024-03-15T15:46:53.447000
55
Views
What is the microcode scoreboard?
Published on
15 March 2024 at 15:46
#x86
#cpu-architecture
#intel
#intel-pmu
#microcoding
60
Views
How to get the number of instructions executed inside a virtual machine from the host?
Published on
03 January 2024 at 05:58
#qemu
#kvm
#perf
#intel-pmu
85
Views
Why does it need to be divided by 9 when calculating UPI bandwidth on the Intel platform using UNC_UPI_TxL_FLITS.ALL_DATA event?
Published on
22 December 2023 at 08:34
#x86
#cpu-architecture
#intel
#perf
#intel-pmu
82
Views
How to count the number of data loaded into the cache but not used?
Published on
06 November 2023 at 13:59
#caching
#x86
#perf
#cpu-cache
#intel-pmu
116
Views
How to count offcore PMU events on an old kernel?
Published on
17 October 2023 at 03:55
#profiling
#perf
#intel-pmu
36
Views
How to collect DMA events (like memory write and read) by perf tool?
Published on
11 October 2023 at 09:44
#performance
#perf
#dma
#intel-pmu
87
Views
Getting count of TLB misses that resulted in memory access in x86-64
Published on
27 September 2023 at 04:26
#x86-64
#cpu-architecture
#intel
#tlb
#intel-pmu
21
Views
Why don’t current tools support collecting memory bandwidth usage data at process granularity?
Published on
12 September 2023 at 03:57
#profiling
#intel-pmu
#memory-bandwidth
153
Views
Is mmap() faster than read() for perf_event_open
Published on
08 September 2023 at 20:42
#c
#mmap
#perf
#intel-pmu
56
Views
How do different monitoring tools calculate memory bandwidth?
Published on
08 September 2023 at 13:19
#performance
#intel
#amd-processor
#intel-pmu
#memory-bandwidth
105
Views
Workload Memory Bandwidth Comparison Inconsistency
Published on
13 August 2023 at 01:26
#x86
#perf
#memory-access
#intel-pmu
#memory-bandwidth
53
Views
Can rdpmc be used to read the fixed-function counters on AMD?
Published on
03 August 2023 at 23:52
#x86
#intel
#performancecounter
#amd-processor
#intel-pmu
38
Views
Measuring ITLB_FLUSH on icelake processors
Published on
06 July 2023 at 15:54
#x86
#cpu
#perf
#tlb
#intel-pmu
72
Views
Which instruction is recorded when an overflow of PMC occurs?
Published on
05 June 2023 at 03:38
#x86
#cpu-architecture
#perf
#intel-pmu
#performance-monitor
153
Views
Don't all loads result in an L1 cache hit (after the data arrives if it initially missed)?
Published on
26 April 2023 at 14:26
#caching
#cpu
#cpu-architecture
#cpu-cache
#intel-pmu
59
Views
Why LLC related performance events share the same event id in perf?
Published on
14 April 2023 at 14:47
#caching
#cpu-architecture
#intel
#perf
#intel-pmu
102
Views
What are the complete sources of L3 misses which aren't counted by the cache-miss event on Skylake?
Published on
12 April 2023 at 06:25
#caching
#cpu-architecture
#intel
#perf
#intel-pmu
76
Views
CPU performance monitor counters cannot be read directly
Published on
13 March 2023 at 03:09
#performance
#x86
#cpu
#cpu-architecture
#intel-pmu
148
Views
Is it possible to sample LOAD and STORE instructions at the same time in Intel PEBS sampling?
Published on
02 December 2022 at 07:15
#linux
#performance
#cpu-architecture
#perf
#intel-pmu
116
Views
Perf Result Conflict During Multiplexing
Published on
19 November 2022 at 02:51
#linux-kernel
#performancecounter
#perf
#memory-access
#intel-pmu
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