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20
Devhide
2024-03-15T11:05:42.203000
128
Views
How CPUs Use the LOCK Prefix to Implement Cache Locking and ensure memory consistency
Published on
15 March 2024 at 11:05
#java
#volatile
#cpu-cache
#memory-barriers
#mesi
133
Views
Can CPU load data from another CPU's cache using LOCK CMPXCHG instruction in x86?
Published on
15 December 2023 at 17:36
#x86
#cpu-architecture
#atomic
#cpu-cache
#mesi
181
Views
How `memory_order_relaxed` is enough in TTAS spinlock for Arm64?
Published on
14 December 2023 at 17:10
#c++
#arm
#memory-barriers
#spinlock
#mesi
128
Views
Invalidation of an Exclusive cache line
Published on
11 December 2023 at 17:07
#cpu-architecture
#cpu-cache
#memory-barriers
#mesi
53
Views
Is it Possible for a Thread to Read Stale Data Due to CPU Core Switching in a Multi-threaded Environment?
Published on
06 September 2023 at 12:58
#multithreading
#mesi
87
Views
Confusing "Memory Barrier Example 1" in 《Memory Barriers: a Hardware View for Software Hackers》？
Published on
03 September 2023 at 17:04
#cpu-cache
#memory-barriers
#lockless
#mesi
87
Views
optimal to flush low-contention atomic from caches?
Published on
24 August 2023 at 18:12
#multithreading
#cpu-architecture
#atomic
#cpu-cache
#mesi
206
Views
How is message queue implemented in cache coherence protocol?
Published on
06 December 2022 at 06:41
#concurrency
#cpu-architecture
#cpu-cache
#memory-barriers
#mesi
343
Views
Does Cache Coherence always prevent reading a stale value? Do invalidation queues allow it?
Published on
27 August 2022 at 06:48
#caching
#cpu-architecture
#cpu-cache
#memory-barriers
#mesi
166
Views
Data races with MESI optimization
Published on
03 June 2022 at 16:31
#caching
#cpu
#cpu-architecture
#memory-barriers
#mesi
180
Views
Shortcomings of cache coherence alternative
Published on
04 April 2022 at 16:19
#cpu-architecture
#cpu-cache
#mesi
140
Views
cache coherence - Why are some steps considered exclusive?
Published on
07 December 2021 at 14:55
#caching
#cpu-architecture
#cpu-cache
#cpu-cores
#mesi
148
Views
how to fix the problem while cpu store buffer cause data unconsistency?
Published on
04 December 2021 at 14:01
#x86-64
#cpu
#memory-barriers
#lock-free
#mesi
86
Views
Cache coherence systems from a timing point of view
Published on
01 December 2021 at 08:46
#caching
#cpu-architecture
#cpu-cache
#memory-barriers
#mesi
225
Views
Cache coherence state machine
Published on
29 November 2021 at 03:08
#caching
#x86
#cpu-architecture
#cpu-cache
#mesi
320
Views
Why is cache coherency important in multi-processor system?
Published on
20 November 2021 at 18:50
#multithreading
#caching
#cpu-architecture
#cpu-cache
#mesi
417
Views
MESI protocol - what keeps cache line in exclusive mode during atomic operations
Published on
24 July 2021 at 06:07
#concurrency
#x86
#atomic
#cpu-architecture
#mesi
299
Views
MSI: When shared and invalid states can occur at the same time
Published on
19 May 2021 at 10:40
#caching
#cpu-architecture
#cpu-cache
#mesi
260
Views
Can MESI protocol auto sync a variable value bewteen cpu cores?
Published on
11 May 2021 at 07:54
#c++
#cpu-architecture
#mesi
259
Views
Is synchronization faster on the same physical CPU core?
Published on
25 April 2021 at 22:36
#multithreading
#synchronization
#hyperthreading
#mesi
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