Question

Should ISR be re-entrant if I provide the same ISR to multiple interrupt lines?

score 18 · Answer 1 · 2023-07-08T23:27:11.490000

18

Views

Should ISR be re-entrant if I provide the same ISR to multiple interrupt lines?

Published on 08 July 2023 at 23:27

score 137 · Answer 2 · 2023-04-13T01:29:54.183000

137

Views

How to start secondary risc-v core in Renode emulator?

Published on 13 April 2023 at 01:29

score 113 · Answer 3 · 2023-02-08T08:47:57.623000

113

Views

How is ARM PPI is triggered and handled by an SMP ARM system?

Published on 08 February 2023 at 08:47

score 523 · Answer 4 · 2022-12-27T00:50:25.970000

523

Views

What is the difference between processor cores and SMP cores?

Published on 27 December 2022 at 00:50

score 227 · Answer 5 · 2022-11-10T11:04:52.540000

227

Views

Why atomic_thread_fence need atomic operation to work correctly

Published on 10 November 2022 at 11:04

score 520 · Answer 6 · 2022-09-10T08:36:16.503000

520

Views

Why Linux distributes threads among NUMA nodes almost equally?

Published on 10 September 2022 at 08:36

score 112 · Answer 7 · 2022-08-04T15:13:50.190000

112

Views

Linux softirq and SMP

Published on 04 August 2022 at 15:13

score 295 · Answer 8 · 2022-03-09T15:16:47.680000

295

Views

Send BLE raw packet through serial port

Published on 09 March 2022 at 15:16

score 71 · Answer 9 · 2022-01-20T09:22:29.337000

71

Views

why does read barrier can causes all effects prior to storage from another cpu be perceptible?

Published on 20 January 2022 at 09:22

score 408 · Answer 10 · 2021-07-05T00:53:13.267000

408

Views

"SMP is not supported on this platform"

Published on 05 July 2021 at 00:53

score 111 · Answer 11 · 2021-04-30T19:21:54.917000

111

Views

Can printf() be made SMP safe?

Published on 30 April 2021 at 19:21

score 261 · Answer 12 · 2021-01-12T13:25:31.587000

261

Views

Is memory reordering equivalent to instruction reordering?

Published on 12 January 2021 at 13:25

score 2.3k · Answer 13 · 2020-12-23T14:05:26.720000

2.3k

Views

rpi-benchmark seems to have crashed my system: SMP : failed to stop secondary CPUs after running

Published on 23 December 2020 at 14:05

score 490 · Answer 14 · 2020-09-23T14:41:12.290000

490

Views

How to invalidate cache on mmap'ed shared memory (multi processor machine)

Published on 23 September 2020 at 14:41

score 122 · Answer 15 · 2020-08-25T09:30:10.727000

122

Views

for_each_possible_cpu macro in vmalloc_init() function, does the code run in only one cpu? or in every cpu?

Published on 25 August 2020 at 09:30

score 1.1k · Answer 16 · 2020-06-15T10:19:48.387000

1.1k

Views

Can't find WSL kernel directory not in /usr/src and not in /lib/modules

Published on 15 June 2020 at 10:19

score 2k · Answer 17 · 2020-05-28T15:41:11.510000

2k

Views

Kinds of IPI for x86 architecture in Linux

Published on 28 May 2020 at 15:41

score 1.2k · Answer 18 · 2020-03-26T02:58:46.097000

1.2k

Views

Confusion around spin_lock_irqsave: in what nested situation is interrupt state kept?

Published on 26 March 2020 at 02:58

score 330 · Answer 19 · 2020-01-09T08:30:20.733000

330

Views

How seastar invoke codes on different cpus?

Published on 09 January 2020 at 08:30

score 286 · Answer 20 · 2019-12-21T20:40:38.350000

286

Views

I have a cpu cache coherency-looking problem that I can't figure out how to fix. Two cpus see different contents of the same memory

Published on 21 December 2019 at 20:40

List Question

Should ISR be re-entrant if I provide the same ISR to multiple interrupt lines?

How to start secondary risc-v core in Renode emulator?

How is ARM PPI is triggered and handled by an SMP ARM system?

What is the difference between processor cores and SMP cores?

Why atomic_thread_fence need atomic operation to work correctly

Why Linux distributes threads among NUMA nodes almost equally?

Linux softirq and SMP

Send BLE raw packet through serial port

why does read barrier can causes all effects prior to storage from another cpu be perceptible?

"SMP is not supported on this platform"

Can printf() be made SMP safe?

Is memory reordering equivalent to instruction reordering?

rpi-benchmark seems to have crashed my system: SMP : failed to stop secondary CPUs after running

How to invalidate cache on mmap'ed shared memory (multi processor machine)

for_each_possible_cpu macro in vmalloc_init() function, does the code run in only one cpu? or in every cpu?

Can't find WSL kernel directory not in /usr/src and not in /lib/modules

Kinds of IPI for x86 architecture in Linux

Confusion around spin_lock_irqsave: in what nested situation is interrupt state kept?

How seastar invoke codes on different cpus?

I have a cpu cache coherency-looking problem that I can't figure out how to fix. Two cpus see different contents of the same memory

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