I am using cocotb to simulate a large SystemVerilog design.
When I run the simulation, I see a very large number of log warnings of the form:
[timestamp] ++BUS CONFLICT++ : top.submodule1.submodule2.submodule3
I believe these warnings are being generated by tristate buses in my design. submodule3 is a tristate driver cell.
When I view traces in simvision, it seems that the tristate buses are working correctly -- there is no drive conflict occurring at any time, and it seems that cocotb is simply raising the warning because the bus exists.
These warnings are a nuisance, and I believe they are reducing my simulation performance. How can I suppress them?
I have searched through online documentation for cocotb and the Github, but I was unable to find how these warnings are being generated.
My expected result is to be able to run my simulation with no "++BUS CONFLICT++" warnings, unless there is an actual drive conflict on the bus.
I am pretty sure that these warnings are not coming from cocotb. They also do not look like they are coming from Xcelium directly, so that leaves something in your design, a model or explicit bus conflict monitor perhaps? Grep your design files for "BUS CONFLICT", then check the lines around where it is generated to see how you can configure its reporting behavior.
Edit: looking at this very old thread seems to suggest that Xcelium (the successor of ncsim) indeed can produce these messages: http://computer-programming-forum.com/41-verilog/2a1617c287267e5e.htm Maybe the way to go is to ask your Cadence FAE.