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20
Devhide
2024-01-15T18:25:30.850000
44
Views
designing a circuit with 3 3-bit inputs and 4 1-bit outputs
Published on
15 January 2024 at 18:25
#boolean
#logical-operators
#boolean-expression
#digital-logic
138
Views
Non Restoring Division in Iverilog
Published on
11 November 2023 at 07:08
#digital-logic
#iverilog
78
Views
How to mitigate / suppress tristate bus conflict warnings with Cocotb?
Published on
22 September 2023 at 20:40
#simulation
#digital-logic
#cocotb
132
Views
Draw Logic Circuits using python's schemdraw
Published on
21 July 2023 at 05:21
#python
#logic
#logical-operators
#digital-logic
#schemdraw
937
Views
How to implement the Boolean function = + ′′ + ′ with NAND and NOT gates
Published on
25 March 2023 at 14:12
#boolean-logic
#boolean-expression
#digital-logic
#booleanquery
92
Views
FPGA Basys 3 State Machine Logic with PMOD ALS Sensor
Published on
17 February 2023 at 22:43
#verilog
#fpga
#state-machine
#digital-logic
118
Views
Understanding the functioning of 'and' and 'or'
Published on
05 February 2023 at 20:36
#python
#boolean
#kaggle
#digital-logic
117
Views
How can I determine the sop and pos part from a combined expression
Published on
02 November 2022 at 05:39
#boolean-logic
#boolean-expression
#digital-logic
655
Views
width mismatch in assignment; target has 10 bits, source has 8 bits error
Published on
15 October 2022 at 07:32
#vhdl
#vivado
#digital-logic
332
Views
Using One's Complement In Place of Directly Subtracting Two Binary Numbers
Published on
28 August 2022 at 01:35
#assembly
#cpu-architecture
#digital-logic
267
Views
How to write ALU control lines?
Published on
16 June 2022 at 01:08
#cpu-architecture
#digital-logic
#alu
113
Views
Multiplication table in VMLab / AVR
Published on
18 April 2022 at 21:27
#avr
#digital-logic
304
Views
VHDL - Upper digit output does not go up from '0000', when implementing two-digit-bcd-counter
Published on
08 March 2022 at 08:50
#vhdl
#fpga
#digital-logic
#hardware
264
Views
Output not as expected when implementing 4-bit SISO register in VHDL
Published on
06 March 2022 at 16:05
#vhdl
#fpga
#digital-logic
#hardware
425
Views
Problem while implementing JK-Flip Flop in VHDL
Published on
02 March 2022 at 05:04
#vhdl
#digital-logic
#hardware
#digital-design
219
Views
How to represent multiple-output logic circuits in tree-based genetic programming
Published on
10 February 2022 at 14:48
#tree
#logic
#genetic-programming
#digital-logic
#s-expression
55
Views
What does the double slash(transition 0 --> 1) mean in SRAM datasheet?
Published on
29 January 2022 at 07:52
#fpga
#digital-logic
286
Views
How to create K-MAP from function
Published on
18 January 2022 at 16:49
#digital-logic
#digital-design
733
Views
How can w’xz + w’yz + x’yz’ + wxy’z be implemented with 4 NOR gates (+ inverters), given d = wyz
Published on
17 January 2022 at 11:58
#digital-logic
#karnaugh-map
#nor
1.3k
Views
Shifting in Verilog for multiplication
Published on
11 January 2022 at 11:59
#verilog
#system-verilog
#fpga
#digital
#digital-logic
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