How to run `make` on a `makefile` target and ignore prerequisites?

Question

Let's say I have a make target abc with prerequisites x, y, and z.

abc: x y z
    echo 'Do something'

Is there not some simple way to run make and ignore the prerequisites, such that it runs abc without first running x, y, and z?

Answer 1

$ make
echo x updated
x updated
echo y updated
y updated
echo z updated
z updated
echo all updated
all updated

$ make noreq=y
echo all updated
all updated

How it's done:

ifdef noreq
req :=
else
req = $(1)
endif

.PHONY: all x y z

all: $(call req,x y z)
    echo $@ updated

x y z:
    echo $@ updated

Note that a GNU Makefile can examine the value of the variable MKCMDGOALS and calculate other variables from that. You could have it that when certain targets are explicitly given on the command line (and thus appear in MKCMDGOALS) then the noreq flags comes into effect, and those targets adjust their behavior with the macro.

CAVEAT: In the noreq mode, the target actually does not have prerequisites, so your rule cannot refer to prerequisites via $^ or $<.