Mod-6 counter using JK flipflop always shows unknown output

Question

I am trying to implement mod-6 counter using mod-8 counter but can't get the required output waveform.

module mod_six_counter(clk,rst,q,qbar);
  input clk;
  input wire rst;
  output wire  [2:0]q;
  output [2:0]qbar;
  assign rst = ~((~q[0])&q[1]&(q[2]));
  jkff ff1(1'b1,1'b1,clk,rst,q[0],qbar[0]);
  jkff ff2(1'b1,1'b1,q[0],rst,q[1],qbar[1]);
  jkff ff3(1'b1,1'b1,q[1],rst,q[2],qbar[2]);
endmodule

module jkff(j,k,clk,rst,q,qbar);
  input j,k,clk,rst;
  output reg q;
  output qbar;
  always@(posedge clk or negedge rst)
  begin
        if (!rst)       q <= 1'b0;
  else begin
    case({j,k})
      2'b00 : q<=q;
      2'b01 : q<=1'b0;
      2'b10 : q<=1'b1;
      2'b11 : q<=~q;
      endcase
    end
  end
     assign  qbar = ~q;
endmodule

Test Bench Code:

module tbmod_sixcounter;
  reg clk,rst;
  wire[2:0] q,qbar;

  mod_six_counter DUT(.clk(clk),.rst(rst),.q(q),.qbar(qbar));

  always #10 clk=~clk;

  initial 
  begin
    clk<=0;
    rst<=0;
    #7 rst<=1;
  end
endmodule

What is the mistake in this code? Can anyone help to solve it? The wave appears simply as xxx.

Answer 1

The problem is that you are making an assignment to a module input port (rst) from within the mod_six_counter module. This causes contention because you are also driving the input port from the testbench, and contention results in x's (unknowns). It is a bad practice make an assignment to an input port inside the module.

If you delete the following line, the x's (unknowns) go away:

  assign rst = ~((~q[0])&q[1]&(q[2]));

Alternately, if you really do want to drive the individual jkff instances with a different reset signal, then you can create a signal with a different name inside the mod_six_counter module, for example:

wire rst_int; // Internal reset

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You can also simplify your code by designing a counter with a single always block. There is no need to design at such a low level of abstraction with Verilog (no need for individual flip-flop modules).