We have an embedded processor (with Linux v5.4 aarch64) connected to an external FPGA through a PCIe Gen3 bus.
Our Linux Processor is root complex and FPGA is an endpoint on the bus. The FPGA has some BARs mapped to Linux for direct read/write operations but also the FPGA provides a DMA as a bus master, and whenever Linux CPU requests, the FPGA DMA streams out a bulk of data through PCIe to Linux Memory and sends an MSI interrupt to the Linux at the end of transfer.
Individual read/write accesses to some registers through BARs, as 8 bit, 16bit, 32bit work fine.
Also when we initiate a DMA transaction standalone, from FPGA to Linux or Linux to FPGA that also works as expected.
But when we initiate a DMA transaction and before completion, if we try to read some other registers on the FPGA through BARs, I get garbage data mostly as 0xFFFFFFFF.
The FPGA DMA as a bus mater can block the transfer until the requested data available on the FPGA.
As I know PCIe is a kind of high level protocol like TCP but I wonder that while a DMA transaction is on going, if I try to read some other registers through BAR mappings, is this something that PCIe bus cannot automatically handle as per their standard?
If not then, what is the proper way of fulfilling such a requirement?