Can a processor have same opcode for different sets of instructions?

Question

I have a processor. Some instruction sets are AND, ADD, ANDI, ADDI. These looks like same but they are not. Can I assign same opcode for looks like same instructions sets as follows screen shot:

or sixth bit is enough to differentiate them?

In actual example of ISA, I have 13 instruction sets (AND, ADD, LD, ST, ANDI, ADDI, CMP, JUMP, JE, JA, JB, JBE, JAE). Because of size of instruction sets, I think number of opcode bits should be 4 bits and also all different instruction sets should have different opcode like ADD 0001, ADDI 0010, AND 0011, and ANDI 0100 etc.

Answer 1

Absolutely. Most CISC CPU assembly languages do this actually. I'll use 6502 Assembly x86 Assembly to illustrate, but it's certainly possible to write your own MIPS assembler that allows this.

    mov eax,[eax]  ;encoded as 8B 00
    mov eax,[ecx]  ;encoded as 8B 01
    mov eax,[edx]  ;encoded as 8B 02
    mov eax,[ebx]  ;encoded as 8B 03

All of these instructions load the eax register indirectly using another register as a pointer to memory. Which register is used depends on the pattern of bits. Not the best example, but it is a thing that many CPUs do.

EDIT: used x86 Assembly for the example now, which doesn't completely change the bytes when using different operation modes for this example.