Question

Mysterious ARM Opcode

score 77 · Answer 1 · 2024-01-14T20:00:02.060000

77

Views

Mysterious ARM Opcode

Published on 14 January 2024 at 20:00

score 276 · Answer 2 · 2023-11-22T13:23:04.787000

276

Views

Disassembling bytecode into opcodes across different EVM versions

Published on 22 November 2023 at 13:23

score 22 · Answer 3 · 2023-09-15T20:53:28.530000

22

Views

Any useful way (amd64) to effect a transfer like this? pc <-- (sp) [Note the absense of auto-decrement]

Published on 15 September 2023 at 20:53

score 61 · Answer 4 · 2023-08-26T11:52:01.150000

61

Views

Explaining LLVM for loop

Published on 26 August 2023 at 11:52

score 22 · Answer 5 · 2023-08-12T03:47:56.420000

22

Views

ANSI C90 68hc11 Assembly Language, Opcode Error Trapping

Published on 12 August 2023 at 03:47

score 63 · Answer 6 · 2023-07-12T16:35:08.777000

63

Views

How can I write a short bitwise code as jmp $ without directives?

Published on 12 July 2023 at 16:35

score 660 · Answer 7 · 2023-06-05T07:01:08.547000

660

Views

Migrations hit an invalid opcode while deploying

Published on 05 June 2023 at 07:01

score 569 · Answer 8 · 2023-05-26T15:53:20.810000

569

Views

System.InvalidProgramException Common Language Runtime detected an invalid program for Reflection

Published on 26 May 2023 at 15:53

score 48 · Answer 9 · 2023-05-07T15:36:37.843000

48

Views

How does the VM OS issue privileged Opcodes without being terminated by the Host OS/CPU?

Published on 07 May 2023 at 15:36

score 130 · Answer 10 · 2023-04-18T11:44:11.883000

130

Views

how to detect the instruction boundary while designing a disassembler?

Published on 18 April 2023 at 11:44

score 486 · Answer 11 · 2023-04-17T13:29:19.567000

486

Views

machine code FF 25 should have 64-bit operand but actually only 32-bit is available

Published on 17 April 2023 at 13:29

score 132 · Answer 12 · 2023-04-12T09:47:22.470000

132

Views

Create a Field using FieldBuilder and add one to Field Value in MethodBuilder ILCode Emit

Published on 12 April 2023 at 09:47

score 129 · Answer 13 · 2023-04-05T06:59:56.003000

129

Views

OPCUA subscribing to all events

Published on 05 April 2023 at 06:59

score 209 · Answer 14 · 2023-03-20T10:48:18.053000

209

Views

How can I using OpCodes and Emit set a parameter to an instantiated Property of type T?

Published on 20 March 2023 at 10:48

score 26 · Answer 15 · 2023-02-25T11:16:15.260000

26

Views

Why MOVZX r64, r/m8 behave like MOVZX r32, r/m8

Published on 25 February 2023 at 11:16

score 258 · Answer 16 · 2023-01-27T22:25:00.567000

258

Views

Opcode differences between MOV r/m32, imm32 and MOV r32, imm32

Published on 27 January 2023 at 22:25

score 88 · Answer 17 · 2023-01-18T09:30:09.657000

88

Views

MSP430 opcode table

Published on 18 January 2023 at 09:30

score 1.1k · Answer 18 · 2022-12-18T02:10:48.857000

1.1k

Views

Reassemble Python bytecode to source (CTF challenge)

Published on 18 December 2022 at 02:10

score 350 · Answer 19 · 2022-12-10T04:40:25.910000

350

Views

How to access content of stack in Python disassembler?

Published on 10 December 2022 at 04:40

score 361 · Answer 20 · 2022-12-07T23:41:32.093000

361

Views

Can a processor have same opcode for different sets of instructions?

Published on 07 December 2022 at 23:41

List Question

Mysterious ARM Opcode

Disassembling bytecode into opcodes across different EVM versions

Any useful way (amd64) to effect a transfer like this? pc <-- (sp) [Note the absense of auto-decrement]

Explaining LLVM for loop

ANSI C90 68hc11 Assembly Language, Opcode Error Trapping

How can I write a short bitwise code as jmp $ without directives?

Migrations hit an invalid opcode while deploying

System.InvalidProgramException Common Language Runtime detected an invalid program for Reflection

How does the VM OS issue privileged Opcodes without being terminated by the Host OS/CPU?

how to detect the instruction boundary while designing a disassembler?

machine code FF 25 should have 64-bit operand but actually only 32-bit is available

Create a Field using FieldBuilder and add one to Field Value in MethodBuilder ILCode Emit

OPCUA subscribing to all events

How can I using OpCodes and Emit set a parameter to an instantiated Property of type T?

Why MOVZX r64, r/m8 behave like MOVZX r32, r/m8

Opcode differences between MOV r/m32, imm32 and MOV r32, imm32

MSP430 opcode table

Reassemble Python bytecode to source (CTF challenge)

How to access content of stack in Python disassembler?

Can a processor have same opcode for different sets of instructions?

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