Continuing my study of cache-as-ram mode for x64 cores: I did not see any reason given in either discussions or documentation whether both of a pair of logical i3 cores during hyperthreading had to be set for cache-as-ram execution, or neither. Is a mix possible, or should I divide this between actual i3 cores?
Can I start one i3 logical core in cache-as-ram mode while it's partner accesses dram?
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